Stochastic rounding of numerical values

ABSTRACT

A method, computer readable medium, and system are disclosed for rounding numerical values. A set of bits from an input value is identified as a rounding value. A second set of bits representing a second value is extracted from the input value and added with the rounding value to produce a sum. The sum is truncated to produce the rounded output value. Thus, the present invention provides a stochastic rounding technique that rounds up an input value as a function of a second value and a rounding value, both of which were obtained from the input value. When the second value and rounding value are obtained from consistent bit locations of the input value, the resulting output value is deterministic. Stochastic rounding, which is deterministic, is advantageously applicable in deep learning applications.

FIELD OF THE INVENTION

The present invention relates to rounding numerical values, and moreparticularly, to circuits for performing stochastic rounding.

BACKGROUND

Reducing precision in representing numerical values for mathematicalcomputations may be beneficial in certain circumstances. For example,32-bit floating-point values can be replaced with less precise 16-bitfloating-point values to reduce circuitry, power, and bandwidth fortraining of neural networks. The reduced precision values require onlyhalf the bandwidth during data transmission and less than half the diearea and power consumption compared with using full precision values.However, the range of values that can be represented using a 16-bitfloating-point format is much smaller than the range of values that canbe represented using a 32-bit floating-point format. Numbers smallerthan the smallest value represented by the 16-bit floating-point formatare lost (i.e., turned to zero).

Stochastic rounding is a method that is conventionally used to extendnumerical range. With traditional rounding, numbers aredeterministically rounded up or down, for example values between 0.5 and1 are rounded up to 1, values below 0.5 are always rounded down to 0.With stochastic rounding, the rounding is instead probabilistic.Specifically, 0.5% has 50% odds of being rounded up to 1 and 50% odds ofbeing rounded down to 0, while 0.1 has 10% odds of being rounded up to 1and 90% odds of being rounded down to 0.

With stochastic rounding, an individual rounding event can actuallyintroduce more error, but on average over a long sequence ofaccumulations, the result will have less error. For example, whenaccumulating 1000 numbers with value 0.1 with traditional rounding aftereach number is accumulated, the result will be zero, whereas withstochastic rounding the result should be closer to the correct answer of100.

Thus while stochastic rounding is preferable when applying an accumulateand round operation over a long series of numerical values, thechallenge is implementing the random rounding behavior of stochasticrounding efficiently in software or hardware. One method could be togenerate a random number for each rounding operation, but that isextremely expensive in terms of additional circuitry and/or powerconsumption. There is a need for addressing these issues and/or otherissues associated with the prior art.

SUMMARY

A method, computer readable medium, and system are disclosed forrounding a numerical value. An input value represented by a first numberof bits is received and a portion of the first number of bits of theinput value is identified as a rounding value represented by a secondnumber of bits. A second value is extracted from the input value and therounding value is aligned with a rounding position within the secondvalue, where the rounding position corresponds to a least significantbit of an output value represented by a third number of bits. Thealigned rounding value and the second value are added to produce a sumand the sum is truncated to produce the output value.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a flowchart of a method for rounding numericalvalues, in accordance with an embodiment.

FIG. 2A illustrates a block diagram of a rounding unit, in accordancewith an embodiment.

FIG. 2B illustrates rounding of a 23-bit mantissa to produce a 10-bitreduced bit width mantissa, in accordance with an embodiment.

FIG. 2C illustrates another block diagram of a rounding unit, inaccordance with an embodiment.

FIG. 2D illustrates another flowchart of a method for rounding numericalvalues, in accordance with an embodiment.

FIG. 3 illustrates a parallel processing unit, in accordance with anembodiment.

FIG. 4A illustrates a general processing cluster within the parallelprocessing unit of FIG. 3, in accordance with an embodiment.

FIG. 4B illustrates a memory partition unit of the parallel processingunit of FIG. 3, in accordance with an embodiment.

FIG. 5A illustrates the streaming multi-processor of FIG. 4A, inaccordance with an embodiment.

FIG. 5B is a conceptual diagram of a processing system implemented usingthe PPU of FIG. 3, in accordance with an embodiment.

FIG. 5C illustrates an exemplary system in which the variousarchitecture and/or functionality of the various previous embodimentsmay be implemented.

DETAILED DESCRIPTION

A new rounding mechanism is described for reducing the bit width of avalue from its original full bit width (N-bits) to a reduced bit width(M-bits). In an embodiment, a portion of the N bits of the value of afloating-point mantissa are used as a rounding value. A roundingposition within the full bit width value is the position of the leastsignificant bit of the reduced bit width value. In other words, bits tothe right of the rounding position will be truncated to perform the bitwidth reduction. The number of fractional bits to the right of therounding position to be truncated may be fixed, computed, orprogrammable. Similarly, the number of bits (M) in the reduced bit widthvalue may be fixed, computed, or programmable. M determines the roundingposition within the N-bit input value. All or less than N-bits of theoriginal input value is used to produce a second value that is summedwith the rounding value.

The rounding value is aligned to the right of the rounding position andadded to the second value to compute a sum. In contrast, whenconventional round-to-nearest is performed, a fixed value is summed withthe full bit width value to compute a sum. In both cases, the fractionalbits to the right of the rounding position within the sum are truncatedto produce the reduced bit width value.

FIG. 1 illustrates a flowchart of a method 100 for rounding numericalvalues, in accordance with an embodiment. Although method 100 isdescribed in the context of a processing unit, the method 100 may alsobe performed by a program, custom circuitry, or by a combination ofcustom circuitry and a program. For example, the method 100 may beexecuted by a GPU (graphics processing unit), CPU (central processingunit), or any processor capable of performing arithmetic computations.Furthermore, persons of ordinary skill in the art will understand thatany system that performs method 100 is within the scope and spirit ofembodiments of the present invention.

At step 110 an input value represented by a first number of bits isreceived. In an embodiment, the input value is represented in afloating-point format comprising an exponent and a mantissa. In anotherembodiment, the input value is represented in a fixed-point format.

At step 120, a portion of the first number of bits of the input value isidentified as a rounding value represented by a second number of bits.In an embodiment, the portion of the first number of bits of the inputvalue are identified within the mantissa. In an embodiment, the portionof the first number of bits of the input value that are identified arethe least significant bits of the mantissa. In an embodiment, theportion of the first number of bits of the input value are identifiedwithin the fixed-point format value. In an embodiment, the portion ofthe first number of bits of the input value that are identified are theleast significant bits of the fixed-point format value. In anotherembodiment, the portion of the first number of bits of the input valuethat are identified are a set of contiguous bits of the input value. Inyet another embodiment, the portion of the first number of bits of theinput value that are identified are a set of bits of the input valuefrom predetermined bit locations of the input value.

At step 130, a second value is extracted from the input value. In anembodiment, the second value is the same value as the input value. Inanother embodiment, the second value is a less precise value of theinput value. In yet another embodiment, the second value is representedby less bits than the input value. At step 140, the rounding value isaligned with a rounding position within the second value, where therounding position corresponds to a least significant bit of an outputvalue represented by a third number of bits. The rounding position isdescribed in more detail in conjunction with FIG. 2B. At step 150, thealigned rounding value and the second value are added to produce a sum.At step 160, a fourth number of bits is truncated from the sum toproduce the output value. In an embodiment, the fourth number of bits isdetermined such that the output value is the reduced bit widthcomprising the third number of bits. In an embodiment, the fourth numberof bits is equal to the second number of bits. In an embodiment, theinput value is a mantissa of a floating-point format number and theoutput value is an integer.

More illustrative information will now be set forth regarding variousoptional architectures and features with which the foregoing frameworkmay be implemented, per the desires of the user. It should be stronglynoted that the following information is set forth for illustrativepurposes and should not be construed as limiting in any manner. Any ofthe following features may be optionally incorporated with or withoutthe exclusion of other features described.

FIG. 2A illustrates a block diagram of a rounding unit 200, inaccordance with an embodiment. The rounding unit 200 includes athreshold comparison unit 210, a multiplexer 215, and an accumulator220. The rounding unit 200 receives a floating-point format valueincluding an exponent and a mantissa of N bits. In an embodiment, thefloating-point format value is represented using an IEEE (Institute ofElectrical and Electronic Engineers) floating-point format. In anembodiment, the mantissa is rounded in accordance with the presentinvention.

The threshold comparison unit 210 compares the floating-point input witha threshold value. When the floating-point input is greater than orequal to the threshold value, a fraction value may be used as a roundingvalue to round the mantissa. The threshold value may be fixed, computed,or programmed. In an embodiment, the threshold value equals the smallestvalue that can be represented using a floating-point format with areduced bit width. In another embodiment, the threshold value equals thelargest value that can be represented using a floating-point format witha reduced bit width.

The threshold comparison unit 210 outputs a select signal to themultiplexer 215 that is used to select either the fraction value or aportion of the input value as the rounding value. In an embodiment, theportion of the mantissa is provided as an input to the multiplexer 215,where the mantissa is a first number of bits (N) and the portion of themantissa includes less than N bits. The rounding unit 200 outputs areduced mantissa having a third number of bits (M), where M is less thanN.

The fraction value may be used to perform conventional IEEE 754-2008rounding. The fraction value may be fixed, computed, or programmed.Otherwise, when the floating-point input is less than (i.e., not greaterthan or equal to) the threshold value, a portion of the mantissa isselected by the multiplexer 215 as a rounding value to round themantissa. The threshold comparison unit 210 extracts a second value fromthe floating-point input. In an embodiment, the second value is aportion of the mantissa having fewer than N bits.

The accumulator 220 receives the second value and the rounding value andproduces the reduced mantissa. The rounding value is aligned with arounding position within the second value. The rounding positioncorresponds to a least significant bit of the reduced mantissa. Thealigned rounding value is summed with the second value to produce a sum.The accumulator 220 truncates a number of bits from the sum to producethe reduced mantissa having a fewer number of bits than the mantissa ofthe input value.

In an embodiment, the input value includes a 23-bit mantissa of afloating-point format number and the output value generated by therounding unit 200 is a 10-bit reduced mantissa. In another embodiment,the input value includes a 23-bit mantissa of a floating-point formatnumber and the output value generated by the rounding unit 200 is a7-bit mantissa. In yet another embodiment, the input value includes a52-bit mantissa of a floating-point format number and the output valuegenerated by the rounding unit 200 is a 23-bit mantissa.

FIG. 2B illustrates rounding of a 23-bit mantissa to produce a 10-bitreduced bit width mantissa, in accordance with an embodiment. In anembodiment, the 23-bit mantissa includes an implied leading one. In anembodiment, the 23-bit mantissa is reduced to a 10-bit reduced mantissaby summing the 8 lsbs (least significant bits) of the 23-bit mantissaaligned with the bits of the 23-bit mantissa that are to the right ofthe lsb of the 10-bit reduced mantissa. As shown in FIG. 2B, the 10most-significant (MS) bits correspond to the reduced bit-width mantissa,where M=10. The 8 least significant (LS) bits (bits 16 through 23) ofthe 23-bit mantissa are used as an 8-bit rounding value that is alignedwith the rounding position and summed with the 23-bit mantissa. A carrybit, generated by summing bits 11 through 18 with bits 16 through 23,increments the 10 MS bits when the carry bit is high. The resulting23-bit sum is truncated to produce the 10-bit reduced mantissa.

In an embodiment, if the sum overflows during rounding, the sum isshifted to the right by one bit and then truncated. In an embodiment,the reduced mantissa is 7 bits. In other embodiments, the reducedmantissa is fewer or more bits. In some embodiment, the number of bitsrepresenting the input mantissa is greater than or less than 23 bits. Inan embodiment, the rounding value or LS bits of the mantissa areoptionally modified before the sum is computed. For example, thefraction value may be XOR'd with the LS bits of the mantissa, thefraction value may be used as a bit rotation count for the LS bits ofthe mantissa, or the fraction value may be used as a mask to selectspecific bits to the right of the rounding position within the mantissato generate the rounding value.

FIG. 2C illustrates another block diagram of a rounding unit 250, inaccordance with an embodiment. The rounding unit 250 includes athreshold comparison unit 212, a rounding value generation unit 225, andthe accumulator 220. The rounding unit 250 receives a floating-pointformat value including an exponent and a mantissa of N bits.

One or more ranges and/or threshold values are defined corresponding todifferent rounding modes and the threshold comparison unit 212 receivesa rounding mode that controls which of the threshold ranges or valuesare compared with the floating-point input. In an embodiment, when thefloating-point input is greater than or equal to the threshold value, afraction value may be used as a rounding value to round the mantissa. Inanother embodiment, when the floating-point input is within or outside athreshold range, the fraction value may be used as a rounding value toround the mantissa. The threshold value and/or the rounding mode may befixed, computed, or programmed.

The threshold comparison unit 212 outputs a select signal to therounding value generation unit 225 that is used to select either thefraction value or a portion of the input value as the rounding value.The rounding mode may be used to modify the rounding value. In anembodiment, the threshold comparison unit 212 extracts and provides aportion of the mantissa as an input to the rounding value generationunit 225, where the mantissa is represented by a first number of bits(N) and the portion of the mantissa includes less than N bits. In anembodiment, the rounding value extracted by the threshold comparisonunit 212 is the LS bits of the mantissa. The rounding unit 250 outputs areduced mantissa having a third number of bits (M), where M is less thanN. In an embodiment, the rounding value selected by the rounding valuegeneration unit 225 is the LS bits of the mantissa.

In an embodiment, the rounding value generation unit 225 modifies therounding value or LS bits of the mantissa are optionally modified beforethe sum is computed. For example, based on the rounding mode, thefraction value may be XOR'd with the LS bits of the mantissa, thefraction value may be used as a bit rotation count for the LS bits ofthe mantissa, or the fraction value may be used as a mask to selectspecific bits to the right of the rounding position within the mantissato generate the rounding value. The rounding mode and/or the fractionvalue may be fixed, computed, or programmed.

As previously described, the accumulator 220 receives the second valueand the rounding value and produces the reduced mantissa. The roundingvalue is aligned with a rounding position within the second value. Therounding position corresponds to a least significant bit of the reducedmantissa. The aligned rounding value is summed with the second value toproduce a sum. The accumulator 220 truncates a number of bits from thesum to produce the reduced mantissa having the third number of bits.

The rounding may be performed using a dedicated instruction, such as aninstruction that converts a value having a first bit-width to a valuehaving a second bit-width, where the second-bit width is less than thefirst bit-width. In an embodiment, one or more of the fraction value,the threshold range, the threshold value, and the rounding mode may beprovided as an operand to the instruction. In an embodiment, thefraction value may be generated by an incrementor. The roundingoperation may be selectively enabled for instructions that performarithmetic operations (e.g., multiply accumulate, sum, etc.) and producea reduced bit-width output. In an embodiment, the rounding value isreturned along with the reduced bit-width value when the instruction(s)is executed.

FIG. 2D illustrates another flowchart of a method 260 for roundingnumerical values, in accordance with an embodiment. Although method 260is described in the context of a processing unit, the method 260 mayalso be performed by a program, custom circuitry, or by a combination ofcustom circuitry and a program. For example, the method 260 may beexecuted by a GPU (graphics processing unit), CPU (central processingunit), or any processor capable of performing arithmetic computations.Furthermore, persons of ordinary skill in the art will understand thatany system that performs method 260 is within the scope and spirit ofembodiments of the present invention.

At step 110 an input value represented by a first number of bits isreceived. In an embodiment, the input value is represented in afloating-point format comprising an exponent and a mantissa. At step265, the threshold comparison unit 212 generates a select signal for theinput value and either a threshold value or threshold range based on arounding mode. In an embodiment, the threshold comparison unit 212compares the input value with the threshold value and generates theselect signal to select a fraction value when the input value is greaterthan the threshold value. In an embodiment, the threshold comparisonunit 212 compares the input value with the threshold value and generatesthe select signal to select the fraction value when the input value isgreater than or equal to the threshold value.

At step 270, the rounding value generation unit 225 determines if theselect signal selects the fraction value, and if not, step 120 iscompleted to identify a portion of the input value to be selected as therounding value before proceeding to step 275. In an embodiment, theportion of the input value is identified by connecting a subset of thewires for the mantissa to the rounding value generation unit 225. If, atstep 270, the rounding value generation unit 225 determines that theselect signal selects the fraction value, the rounding value generationunit 225 proceeds directly to step 275. At step 275, the rounding valuegeneration unit 225 selects a rounding value according to the selectsignal. At step 280, the rounding value generation unit 225 modifies therounding value. The rounding value may be modified based on the fractionvalue and/or the rounding mode. Steps 130 through 160 are completed aspreviously described.

An advantage of using a portion of the input value to perform therounding operation is that the results for a given input value aredeterministic. Specifically, the same output value will be produced fora particular input value regardless of when the rounding operation isperformed. In contrast, when a random value is used to perform therounding operation, the results are not necessarily deterministic.Compared with generating a random value, using a portion of the inputvalue also requires less circuitry. Therefore, the benefit of stochasticrounding (reduced error for successive accumulations) may be achievedwithout requiring generation of a random value.

Parallel Processing Architecture

FIG. 3 illustrates a parallel processing unit (PPU) 300, in accordancewith an embodiment. In an embodiment, the PPU 300 is a multi-threadedprocessor that is implemented on one or more integrated circuit devices.The PPU 300 is a latency hiding architecture designed to process manythreads in parallel. A thread (i.e., a thread of execution) is aninstantiation of a set of instructions configured to be executed by thePPU 300. In an embodiment, the PPU 300 is a graphics processing unit(GPU) configured to implement a graphics rendering pipeline forprocessing three-dimensional (3D) graphics data in order to generatetwo-dimensional (2D) image data for display on a display device such asa liquid crystal display (LCD) device. In other embodiments, the PPU 300may be utilized for performing general-purpose computations. While oneexemplary parallel processor is provided herein for illustrativepurposes, it should be strongly noted that such processor is set forthfor illustrative purposes only, and that any processor may be employedto supplement and/or substitute for the same.

One or more PPUs 300 may be configured to accelerate thousands of HighPerformance Computing (HPC), data center, and machine learningapplications. The PPU 300 may be configured to accelerate numerous deeplearning systems and applications including autonomous vehicleplatforms, deep learning, high-accuracy speech, image, and textrecognition systems, intelligent video analytics, molecular simulations,drug discovery, disease diagnosis, weather forecasting, big dataanalytics, astronomy, molecular dynamics simulation, financial modeling,robotics, factory automation, real-time language translation, onlinesearch optimizations, and personalized user recommendations, and thelike.

As shown in FIG. 3, the PPU 300 includes an Input/Output (I/O) unit 305,a front end unit 315, a scheduler unit 320, a work distribution unit325, a hub 330, a crossbar (Xbar) 370, one or more general processingclusters (GPCs) 350, and one or more partition units 380. The PPU 300may be connected to a host processor or other PPUs 300 via one or morehigh-speed NVLink 310 interconnect. The PPU 300 may be connected to ahost processor or other peripheral devices via an interconnect 302. ThePPU 300 may also be connected to a local memory comprising a number ofmemory devices 304. In an embodiment, the local memory may comprise anumber of dynamic random access memory (DRAM) devices. The DRAM devicesmay be configured as a high-bandwidth memory (HBM) subsystem, withmultiple DRAM dies stacked within each device.

The NVLink 310 interconnect enables systems to scale and include one ormore PPUs 300 combined with one or more CPUs, supports cache coherencebetween the PPUs 300 and CPUs, and CPU mastering. Data and/or commandsmay be transmitted by the NVLink 310 through the hub 330 to/from otherunits of the PPU 300 such as one or more copy engines, a video encoder,a video decoder, a power management unit, etc. (not explicitly shown).The NVLink 310 is described in more detail in conjunction with FIG. 5B.

The I/O unit 305 is configured to transmit and receive communications(i.e., commands, data, etc.) from a host processor (not shown) over theinterconnect 302. The I/O unit 305 may communicate with the hostprocessor directly via the interconnect 302 or through one or moreintermediate devices such as a memory bridge. In an embodiment, the I/Ounit 305 may communicate with one or more other processors, such as oneor more of the PPUs 300 via the interconnect 302. In an embodiment, theI/O unit 305 implements a Peripheral Component Interconnect Express(PCIe) interface for communications over a PCIe bus and the interconnect302 is a PCIe bus. In alternative embodiments, the I/O unit 305 mayimplement other types of well-known interfaces for communicating withexternal devices.

The I/O unit 305 decodes packets received via the interconnect 302. Inan embodiment, the packets represent commands configured to cause thePPU 300 to perform various operations. The I/O unit 305 transmits thedecoded commands to various other units of the PPU 300 as the commandsmay specify. For example, some commands may be transmitted to the frontend unit 315. Other commands may be transmitted to the hub 330 or otherunits of the PPU 300 such as one or more copy engines, a video encoder,a video decoder, a power management unit, etc. (not explicitly shown).In other words, the I/O unit 305 is configured to route communicationsbetween and among the various logical units of the PPU 300.

In an embodiment, a program executed by the host processor encodes acommand stream in a buffer that provides workloads to the PPU 300 forprocessing. A workload may comprise several instructions and data to beprocessed by those instructions. The buffer is a region in a memory thatis accessible (i.e., read/write) by both the host processor and the PPU300. For example, the the I/O unit 305 may be configured to access thebuffer in a system memory connected to the interconnect 302 via memoryrequests transmitted over the interconnect 302. In an embodiment, thehost processor writes the command stream to the buffer and thentransmits a pointer to the start of the command stream to the PPU 300.The front end unit 315 receives pointers to one or more command streams.The front end unit 315 manages the one or more streams, reading commandsfrom the streams and forwarding commands to the various units of the PPU300.

The front end unit 315 is coupled to a scheduler unit 320 thatconfigures the various GPCs 350 to process tasks defined by the one ormore streams. The scheduler unit 320 is configured to track stateinformation related to the various tasks managed by the scheduler unit320. The state may indicate which GPC 350 a task is assigned to, whetherthe task is active or inactive, a priority level associated with thetask, and so forth. The scheduler unit 320 manages the execution of aplurality of tasks on the one or more GPCs 350.

The scheduler unit 320 is coupled to a work distribution unit 325 thatis configured to dispatch tasks for execution on the GPCs 350. The workdistribution unit 325 may track a number of scheduled tasks receivedfrom the scheduler unit 320. In an embodiment, the work distributionunit 325 manages a pending task pool and an active task pool for each ofthe GPCs 350. The pending task pool may comprise a number of slots(e.g., 32 slots) that contain tasks assigned to be processed by aparticular GPC 350. The active task pool may comprise a number of slots(e.g., 4 slots) for tasks that are actively being processed by the GPCs350. As a GPC 350 finishes the execution of a task, that task is evictedfrom the active task pool for the GPC 350 and one of the other tasksfrom the pending task pool is selected and scheduled for execution onthe GPC 350. If an active task has been idle on the GPC 350, such aswhile waiting for a data dependency to be resolved, then the active taskmay be evicted from the GPC 350 and returned to the pending task poolwhile another task in the pending task pool is selected and scheduledfor execution on the GPC 350.

The work distribution unit 325 communicates with the one or more GPCs350 via XBar 370. The XBar 370 is an interconnect network that couplesmany of the units of the PPU 300 to other units of the PPU 300. Forexample, the XBar 370 may be configured to couple the work distributionunit 325 to a particular GPC 350. Although not shown explicitly, one ormore other units of the PPU 300 may also be connected to the XBar 370via the hub 330.

The tasks are managed by the scheduler unit 320 and dispatched to a GPC350 by the work distribution unit 325. The GPC 350 is configured toprocess the task and generate results. The results may be consumed byother tasks within the GPC 350, routed to a different GPC 350 via theXBar 370, or stored in the memory 304. The results can be written to thememory 304 via the partition units 380, which implement a memoryinterface for reading and writing data to/from the memory 304. Theresults can be transmitted to another PPU 304 or CPU via the NVLink 310.In an embodiment, the PPU 300 includes a number U of partition units 380that is equal to the number of separate and distinct memory devices 304coupled to the PPU 300. A partition unit 380 will be described in moredetail below in conjunction with FIG. 4B.

In an embodiment, a host processor executes a driver kernel thatimplements an application programming interface (API) that enables oneor more applications executing on the host processor to scheduleoperations for execution on the PPU 300. In an embodiment, multiplecompute applications are simultaneously executed by the PPU 300 and thePPU 300 provides isolation, quality of service (QoS), and independentaddress spaces for the multiple compute applications. An application maygenerate instructions (i.e., API calls) that cause the driver kernel togenerate one or more tasks for execution by the PPU 300. The driverkernel outputs tasks to one or more streams being processed by the PPU300. Each task may comprise one or more groups of related threads,referred to herein as a warp. In an embodiment, a warp comprises 32related threads that may be executed in parallel. Cooperating threadsmay refer to a plurality of threads including instructions to performthe task and that may exchange data through shared memory. Threads andcooperating threads are described in more detail in conjunction withFIG. 5A.

FIG. 4A illustrates a GPC 350 of the PPU 300 of FIG. 3, in accordancewith an embodiment. As shown in FIG. 4A, each GPC 350 includes a numberof hardware units for processing tasks. In an embodiment, each GPC 350includes a pipeline manager 410, a pre-raster operations unit (PROP)415, a raster engine 425, a work distribution crossbar (WDX) 480, amemory management unit (MMU) 490, and one or more Data ProcessingClusters (DPCs) 420. It will be appreciated that the GPC 350 of FIG. 4Amay include other hardware units in lieu of or in addition to the unitsshown in FIG. 4A.

In an embodiment, the operation of the GPC 350 is controlled by thepipeline manager 410. The pipeline manager 410 manages the configurationof the one or more DPCs 420 for processing tasks allocated to the GPC350. In an embodiment, the pipeline manager 410 may configure at leastone of the one or more DPCs 420 to implement at least a portion of agraphics rendering pipeline. For example, a DPC 420 may be configured toexecute a vertex shader program on the programmable streamingmultiprocessor (SM) 440. The pipeline manager 410 may also be configuredto route packets received from the work distribution unit 325 to theappropriate logical units within the GPC 350. For example, some packetsmay be routed to fixed function hardware units in the PROP 415 and/orraster engine 425 while other packets may be routed to the DPCs 420 forprocessing by the primitive engine 435 or the SM 440. In an embodiment,the pipeline manager 410 may configure at least one of the one or moreDPCs 420 to implement a neural network model and/or a computingpipeline.

The PROP unit 415 is configured to route data generated by the rasterengine 425 and the DPCs 420 to a Raster Operations (ROP) unit, describedin more detail in conjunction with FIG. 4B. The PROP unit 415 may alsobe configured to perform optimizations for color blending, organizepixel data, perform address translations, and the like.

The raster engine 425 includes a number of fixed function hardware unitsconfigured to perform various raster operations. In an embodiment, theraster engine 425 includes a setup engine, a coarse raster engine, aculling engine, a clipping engine, a fine raster engine, and a tilecoalescing engine. The setup engine receives transformed vertices andgenerates plane equations associated with the geometric primitivedefined by the vertices. The plane equations are transmitted to thecoarse raster engine to generate coverage information (e.g., an x,ycoverage mask for a tile) for the primitive. The output of the coarseraster engine is transmitted to the culling engine where fragmentsassociated with the primitive that fail a z-test are culled, andnon-culled fragments are transmitted to a clipping engine wherefragments lying outside a viewing frustum are clipped. Those fragmentsthat survive clipping and culling may be passed to the fine rasterengine to generate attributes for the pixel fragments based on the planeequations generated by the setup engine. The output of the raster engine425 comprises fragments to be processed, for example, by a fragmentshader implemented within a DPC 420.

Each DPC 420 included in the GPC 350 includes an M-Pipe Controller (MPC)430, a primitive engine 435, and one or more SMs 440. The MPC 430controls the operation of the DPC 420, routing packets received from thepipeline manager 410 to the appropriate units in the DPC 420. Forexample, packets associated with a vertex may be routed to the primitiveengine 435, which is configured to fetch vertex attributes associatedwith the vertex from the memory 304. In contrast, packets associatedwith a shader program may be transmitted to the SM 440.

The SM 440 comprises a programmable streaming processor that isconfigured to process tasks represented by a number of threads. Each SM440 is multi-threaded and configured to execute a plurality of threads(e.g., 32 threads) from a particular group of threads concurrently. Inan embodiment, the SM 440 implements a SIMD (Single-Instruction,Multiple-Data) architecture where each thread in a group of threads(i.e., a warp) is configured to process a different set of data based onthe same set of instructions. All threads in the group of threadsexecute the same instructions. In another embodiment, the SM 440implements a SIMT (Single-Instruction, Multiple Thread) architecturewhere each thread in a group of threads is configured to process adifferent set of data based on the same set of instructions, but whereindividual threads in the group of threads are allowed to diverge duringexecution. In an embodiment, a program counter, call stack, andexecution state is maintained for each warp, enabling concurrencybetween warps and serial execution within warps when threads within thewarp diverge. In another embodiment, a program counter, call stack, andexecution state is maintained for each individual thread, enabling equalconcurrency between all threads, within and between warps. Whenexecution state is maintained for each individual thread, threadsexecuting the same instructions may be converged and executed inparallel for maximum efficiency. The SM 440 will be described in moredetail below in conjunction with FIG. 5A.

The MMU 490 provides an interface between the GPC 350 and the partitionunit 380. The MMU 490 may provide translation of virtual addresses intophysical addresses, memory protection, and arbitration of memoryrequests. In an embodiment, the MMU 490 provides one or more translationlookaside buffers (TLBs) for performing translation of virtual addressesinto physical addresses in the memory 304.

FIG. 4B illustrates a memory partition unit 380 of the PPU 300 of FIG.3, in accordance with an embodiment. As shown in FIG. 4B, the memorypartition unit 380 includes a Raster Operations (ROP) unit 450, a leveltwo (L2) cache 460, and a memory interface 470. The memory interface 470is coupled to the memory 304. Memory interface 470 may implement 32, 64,128, 1024-bit data buses, or the like, for high-speed data transfer. Inan embodiment, the PPU 300 incorporates U memory interfaces 470, onememory interface 470 per pair of partition units 380, where each pair ofpartition units 380 is connected to a corresponding memory device 304.For example, PPU 300 may be connected to up to Y memory devices 304,such as high bandwidth memory stacks or graphics double-data-rate,version 5, synchronous dynamic random access memory, or other types ofpersistent storage.

In an embodiment, the memory interface 470 implements an HBM2 memoryinterface and Y equals half U. In an embodiment, the HBM2 memory stacksare located on the same physical package as the PPU 300, providingsubstantial power and area savings compared with conventional GDDR5SDRAM systems. In an embodiment, each HBM2 stack includes four memorydies and Y equals 4, with HBM2 stack including two 128-bit channels perdie for a total of 8 channels and a data bus width of 1024 bits.

In an embodiment, the memory 304 supports Single-Error CorrectingDouble-Error Detecting (SECDED) Error Correction Code (ECC) to protectdata. ECC provides higher reliability for compute applications that aresensitive to data corruption. Reliability is especially important inlarge-scale cluster computing environments where PPUs 300 process verylarge datasets and/or run applications for extended periods.

In an embodiment, the PPU 300 implements a multi-level memory hierarchy.In an embodiment, the memory partition unit 380 supports a unifiedmemory to provide a single unified virtual address space for CPU and PPU300 memory, enabling data sharing between virtual memory systems. In anembodiment the frequency of accesses by a PPU 300 to memory located onother processors is traced to ensure that memory pages are moved to thephysical memory of the PPU 300 that is accessing the pages morefrequently. In an embodiment, the NVLink 310 supports addresstranslation services allowing the PPU 300 to directly access a CPU'spage tables and providing full access to CPU memory by the PPU 300.

In an embodiment, copy engines transfer data between multiple PPUs 300or between PPUs 300 and CPUs. The copy engines can generate page faultsfor addresses that are not mapped into the page tables. The memorypartition unit 380 can then service the page faults, mapping theaddresses into the page table, after which the copy engine can performthe transfer. In a conventional system, memory is pinned (i.e.,non-pageable) for multiple copy engine operations between multipleprocessors, substantially reducing the available memory. With hardwarepage faulting, addresses can be passed to the copy engines withoutworrying if the memory pages are resident, and the copy process istransparent.

Data from the memory 304 or other system memory may be fetched by thememory partition unit 380 and stored in the L2 cache 460, which islocated on-chip and is shared between the various GPCs 350. As shown,each memory partition unit 380 includes a portion of the L2 cache 460associated with a corresponding memory device 304. Lower level cachesmay then be implemented in various units within the GPCs 350. Forexample, each of the SMs 440 may implement a level one (L1) cache. TheL1 cache is private memory that is dedicated to a particular SM 440.Data from the L2 cache 460 may be fetched and stored in each of the L1caches for processing in the functional units of the SMs 440. The L2cache 460 is coupled to the memory interface 470 and the XBar 370.

The ROP unit 450 performs graphics raster operations related to pixelcolor, such as color compression, pixel blending, and the like. The ROPunit 450 also implements depth testing in conjunction with the rasterengine 425, receiving a depth for a sample location associated with apixel fragment from the culling engine of the raster engine 425. Thedepth is tested against a corresponding depth in a depth buffer for asample location associated with the fragment. If the fragment passes thedepth test for the sample location, then the ROP unit 450 updates thedepth buffer and transmits a result of the depth test to the rasterengine 425. It will be appreciated that the number of partition units380 may be different than the number of GPCs 350 and, therefore, eachROP unit 450 may be coupled to each of the GPCs 350. The ROP unit 450tracks packets received from the different GPCs 350 and determines whichGPC 350 that a result generated by the ROP unit 450 is routed to throughthe Xbar 370. Although the ROP unit 450 is included within the memorypartition unit 380 in FIG. 4B, in other embodiment, the ROP unit 450 maybe outside of the memory partition unit 380. For example, the ROP unit450 may reside in the GPC 350 or another unit.

FIG. 5A illustrates the streaming multi-processor 440 of FIG. 4A, inaccordance with an embodiment. As shown in FIG. 5A, the SM 440 includesan instruction cache 505, one or more scheduler units 510, a registerfile 520, one or more processing cores 550, one or more special functionunits (SFUs) 552, one or more load/store units (LSUs) 554, aninterconnect network 580, a shared memory/L1 cache 570.

As described above, the work distribution unit 325 dispatches tasks forexecution on the GPCs 350 of the PPU 300. The tasks are allocated to aparticular DPC 420 within a GPC 350 and, if the task is associated witha shader program, the task may be allocated to an SM 440. The schedulerunit 510 receives the tasks from the work distribution unit 325 andmanages instruction scheduling for one or more thread blocks assigned tothe SM 440. The scheduler unit 510 schedules thread blocks for executionas warps of parallel threads, where each thread block is allocated atleast one warp. In an embodiment, each warp executes 32 threads. Thescheduler unit 510 may manage a plurality of different thread blocks,allocating the warps to the different thread blocks and then dispatchinginstructions from the plurality of different cooperative groups to thevarious functional units (i.e., cores 550, SFUs 552, and LSUs 554)during each clock cycle.

Cooperative Groups is a programming model for organizing groups ofcommunicating threads that allows developers to express the granularityat which threads are communicating, enabling the expression of richer,more efficient parallel decompositions. Cooperative launch APIs supportsynchronization amongst thread blocks for the execution of parallelalgorithms. Conventional programming models provide a single, simpleconstruct for synchronizing cooperating threads: a barrier across allthreads of a thread block (i.e., the syncthreads( ) function). However,programmers would often like to define groups of threads at smaller thanthread block granularities and synchronize within the defined groups toenable greater performance, design flexibility, and software reuse inthe form of collective group-wide function interfaces.

Cooperative Groups enables programmers to define groups of threadsexplicitly at sub-block (i.e., as small as a single thread) andmulti-block granularities, and to perform collective operations such assynchronization on the threads in a cooperative group. The programmingmodel supports clean composition across software boundaries, so thatlibraries and utility functions can synchronize safely within theirlocal context without having to make assumptions about convergence.Cooperative Groups primitives enable new patterns of cooperativeparallelism, including producer-consumer parallelism, opportunisticparallelism, and global synchronization across an entire grid of threadblocks.

A dispatch unit 515 is configured to transmit instructions to one ormore of the functional units. In the embodiment, the scheduler unit 510includes two dispatch units 515 that enable two different instructionsfrom the same warp to be dispatched during each clock cycle. Inalternative embodiments, each scheduler unit 510 may include a singledispatch unit 515 or additional dispatch units 515.

Each SM 440 includes a register file 520 that provides a set ofregisters for the functional units of the SM 440. In an embodiment, theregister file 520 is divided between each of the functional units suchthat each functional unit is allocated a dedicated portion of theregister file 520. In another embodiment, the register file 520 isdivided between the different warps being executed by the SM 440. Theregister file 520 provides temporary storage for operands connected tothe data paths of the functional units.

Each SM 440 comprises L processing cores 550. In an embodiment, the SM440 includes a large number (e.g., 128, etc.) of distinct processingcores 550. Each core 550 may include a fully-pipelined,single-precision, double-precision, and/or mixed precision processingunit that includes a floating-point arithmetic logic unit and an integerarithmetic logic unit. In an embodiment, the floating-point arithmeticlogic units implement the IEEE 754-2008 standard for floating-pointarithmetic. In an embodiment, the cores 550 include 64 single-precision(32-bit) floating-point cores, 64 integer cores, 32 double-precision(64-bit) floating-point cores, and 8 tensor cores. In an embodiment, thecores 550 are configured to perform rounding operations using the method100 or 260.

Tensor cores are configured to perform matrix operations, and, in anembodiment, one or more tensor cores are included in the cores 550. Inparticular, the tensor cores are configured to perform deep learningmatrix arithmetic, such as convolution operations for neural networktraining and inferencing. In an embodiment, each tensor core operates ona 4×4 matrix and performs a matrix multiply and accumulate operationD=A×B+C, where A, B, C, and D are 4×4 matrices. In an embodiment, thetensor cores are configured to perform rounding operations using themethod 100 or 260.

In an embodiment, the matrix multiply inputs A and B are 16-bitfloating-point matrices, while the accumulation matrices C and D may be16-bit floating-point or 32-bit floating-point matrices. Tensor Coresoperate on 16-bit floating-point input data with 32-bit floating-pointaccumulation. The 16-bit floating-point multiply requires 64 operationsand results in a full precision product that is then accumulated using32-bit floating-point addition with the other intermediate products fora 4×4×4 matrix multiply. In practice, Tensor Cores are used to performmuch larger two-dimensional or higher dimensional matrix operations,built up from these smaller elements. An API, such as CUDA 9 C++ API,exposes specialized matrix load, matrix multiply and accumulate, andmatrix store operations to efficiently use Tensor Cores from a CUDA-C++program. At the CUDA level, the warp-level interface assumes 16×16 sizematrices spanning all 32 threads of the warp.

Each SM 440 also comprises M SFUs 552 that perform special functions(e.g., attribute evaluation, reciprocal square root, and the like). Inan embodiment, the SFUs 552 are configured to perform roundingoperations using the method 100 or 260. In an embodiment, the SFUs 552may include a tree traversal unit configured to traverse a hierarchicaltree data structure. In an embodiment, the SFUs 552 may include textureunit configured to perform texture map filtering operations. In anembodiment, the texture units are configured to load texture maps (e.g.,a 2D array of texels) from the memory 304 and sample the texture maps toproduce sampled texture values for use in shader programs executed bythe SM 440. In an embodiment, the texture maps are stored in the sharedmemory/L1 cache 470. The texture units implement texture operations suchas filtering operations using mip-maps (i.e., texture maps of varyinglevels of detail). In an embodiment, each SM 340 includes two textureunits.

Each SM 440 also comprises N LSUs 554 that implement load and storeoperations between the shared memory/L1 cache 570 and the register file520. Each SM 440 includes an interconnect network 580 that connects eachof the functional units to the register file 520 and the LSU 554 to theregister file 520, shared memory/L1 cache 570. In an embodiment, theinterconnect network 580 is a crossbar that can be configured to connectany of the functional units to any of the registers in the register file520 and connect the LSUs 554 to the register file and memory locationsin shared memory/L1 cache 570.

The shared memory/L1 cache 570 is an array of on-chip memory that allowsfor data storage and communication between the SM 440 and the primitiveengine 435 and between threads in the SM 440. In an embodiment, theshared memory/L1 cache 570 comprises 128 KB of storage capacity and isin the path from the SM 440 to the partition unit 380. The sharedmemory/L1 cache 570 can be used to cache reads and writes. One or moreof the shared memory/L1 cache 570, L2 cache 460, and memory 304 arebacking stores.

Combining data cache and shared memory functionality into a singlememory block provides the best overall performance for both types ofmemory accesses. The capacity is usable as a cache by programs that donot use shared memory. For example, if shared memory is configured touse half of the capacity, texture and load/store operations can use theremaining capacity. Integration within the shared memory/L1 cache 570enables the shared memory/L1 cache 570 to function as a high-throughputconduit for streaming data while simultaneously providing high-bandwidthand low-latency access to frequently reused data.

When configured for general purpose parallel computation, a simplerconfiguration can be used compared with graphics processing.Specifically, the fixed function graphics processing units shown in FIG.3, are bypassed, creating a much simpler programming model. In thegeneral purpose parallel computation configuration, the workdistribution unit 325 assigns and distributes blocks of threads directlyto the DPCs 420. The threads in a block execute the same program, usinga unique thread ID in the calculation to ensure each thread generatesunique results, using the SM 440 to execute the program and performcalculations, shared memory/L1 cache 570 to communicate between threads,and the LSU 554 to read and write global memory through the sharedmemory/L1 cache 570 and the memory partition unit 380. When configuredfor general purpose parallel computation, the SM 440 can also writecommands that the scheduler unit 320 can use to launch new work on theDPCs 420.

The PPU 300 may be included in a desktop computer, a laptop computer, atablet computer, servers, supercomputers, a smart-phone (e.g., awireless, hand-held device), personal digital assistant (PDA), a digitalcamera, a vehicle, a head mounted display, a hand-held electronicdevice, and the like. In an embodiment, the PPU 300 is embodied on asingle semiconductor substrate. In another embodiment, the PPU 300 isincluded in a system-on-a-chip (SoC) along with one or more otherdevices such as additional PPUs 300, the memory 204, a reducedinstruction set computer (RISC) CPU, a memory management unit (MMU), adigital-to-analog converter (DAC), and the like.

In an embodiment, the PPU 300 may be included on a graphics card thatincludes one or more memory devices 304. The graphics card may beconfigured to interface with a PCIe slot on a motherboard of a desktopcomputer. In yet another embodiment, the PPU 300 may be an integratedgraphics processing unit (iGPU) or parallel processor included in thechipset of the motherboard.

Exemplary Computing System

Systems with multiple GPUs and CPUs are used in a variety of industriesas developers expose and leverage more parallelism in applications suchas artificial intelligence computing. High-performance GPU-acceleratedsystems with tens to many thousands of compute nodes are deployed indata centers, research facilities, and supercomputers to solve everlarger problems. As the number of processing devices within thehigh-performance systems increases, the communication and data transfermechanisms need to scale to support the increased bandwidth.

FIG. 5B is a conceptual diagram of a processing system 500 implementedusing the PPU 300 of FIG. 3, in accordance with an embodiment. Theexemplary system 565 may be configured to implement the method 100 shownin FIG. 1. The processing system 500 includes a CPU 530, switch 510, andmultiple PPUs 300 each and respective memories 304. The NVLink 310provides high-speed communication links between each of the PPUs 300.Although a particular number of NVLink 310 and interconnect 302connections are illustrated in FIG. 5B, the number of connections toeach PPU 300 and the CPU 530 may vary. The switch 510 interfaces betweenthe interconnect 302 and the CPU 530. The PPUs 300, memories 304, andNVLinks 310 may be situated on a single semiconductor platform to form aparallel processing module 525. In an embodiment, the switch 510supports two or more protocols to interface between various differentconnections and/or links.

In another embodiment (not shown), the NVLink 310 provides one or morehigh-speed communication links between each of the PPUs 300 and the CPU530 and the switch 510 interfaces between the interconnect 302 and eachof the PPUs 300. The PPUs 300, memories 304, and interconnect 302 may besituated on a single semiconductor platform to form a parallelprocessing module 525. In yet another embodiment (not shown), theinterconnect 302 provides one or more communication links between eachof the PPUs 300 and the CPU 530 and the switch 510 interfaces betweeneach of the PPUs 300 using the NVLink 310 to provide one or morehigh-speed communication links between the PPUs 300. In anotherembodiment (not shown), the NVLink 310 provides one or more high-speedcommunication links between the PPUs 300 and the CPU 530 through theswitch 510. In yet another embodiment (not shown), the interconnect 302provides one or more communication links between each of the PPUs 300directly. One or more of the NVLink 310 high-speed communication linksmay be implemented as a physical NVLink interconnect or either anon-chip or on-die interconnect using the same protocol as the NVLink310.

In the context of the present description, a single semiconductorplatform may refer to a sole unitary semiconductor-based integratedcircuit fabricated on a die or chip. It should be noted that the termsingle semiconductor platform may also refer to multi-chip modules withincreased connectivity which simulate on-chip operation and makesubstantial improvements over utilizing a conventional busimplementation. Of course, the various circuits or devices may also besituated separately or in various combinations of semiconductorplatforms per the desires of the user. Alternately, the parallelprocessing module 525 may be implemented as a circuit board substrateand each of the PPUs 300 and/or memories 304 may be packaged devices. Inan embodiment, the CPU 530, switch 510, and the parallel processingmodule 525 are situated on a single semiconductor platform.

In an embodiment, the signaling rate of each NVLink 310 is 20 to 25Gigabits/second and each PPU 300 includes six NVLink 310 interfaces (asshown in FIG. 5B, five NVLink 310 interfaces are included for each PPU300). Each NVLink 310 provides a data transfer rate of 25Gigabytes/second in each direction, with six links providing 300Gigabytes/second. The NVLinks 310 can be used exclusively for PPU-to-PPUcommunication as shown in FIG. 5B, or some combination of PPU-to-PPU andPPU-to-CPU, when the CPU 530 also includes one or more NVLink 310interfaces.

In an embodiment, the NVLink 310 allows direct load/store/atomic accessfrom the CPU 530 to each PPU's 300 memory 304. In an embodiment, theNVLink 310 supports coherency operations, allowing data read from thememories 304 to be stored in the cache hierarchy of the CPU 530,reducing cache access latency for the CPU 530. In an embodiment, theNVLink 310 includes support for Address Translation Services (ATS),allowing the PPU 300 to directly access page tables within the CPU 530.One or more of the NVLinks 310 may also be configured to operate in alow-power mode.

FIG. 5C illustrates an exemplary system 565 in which the variousarchitecture and/or functionality of the various previous embodimentsmay be implemented. The exemplary system 565 may be configured toimplement the method 100 shown in FIG. 1 or the method 260 shown in FIG.2D.

As shown, a system 565 is provided including at least one centralprocessing unit 530 that is connected to a communication bus 575. Thecommunication bus 575 may be implemented using any suitable protocol,such as PCI (Peripheral Component Interconnect), PCI-Express, AGP(Accelerated Graphics Port), HyperTransport, or any other bus orpoint-to-point communication protocol(s). The system 565 also includes amain memory 540. Control logic (software) and data are stored in themain memory 540 which may take the form of random access memory (RAM).

The system 565 also includes input devices 560, the parallel processingsystem 525, and display devices 545, i.e. a conventional CRT (cathoderay tube), LCD (liquid crystal display), LED (light emitting diode),plasma display or the like. User input may be received from the inputdevices 560, e.g., keyboard, mouse, touchpad, microphone, and the like.Each of the foregoing modules and/or devices may even be situated on asingle semiconductor platform to form the system 565. Alternately, thevarious modules may also be situated separately or in variouscombinations of semiconductor platforms per the desires of the user.

Further, the system 565 may be coupled to a network (e.g., atelecommunications network, local area network (LAN), wireless network,wide area network (WAN) such as the Internet, peer-to-peer network,cable network, or the like) through a network interface 535 forcommunication purposes.

The system 565 may also include a secondary storage (not shown). Thesecondary storage 610 includes, for example, a hard disk drive and/or aremovable storage drive, representing a floppy disk drive, a magnetictape drive, a compact disk drive, digital versatile disk (DVD) drive,recording device, universal serial bus (USB) flash memory. The removablestorage drive reads from and/or writes to a removable storage unit in awell-known manner.

Computer programs, or computer control logic algorithms, may be storedin the main memory 540 and/or the secondary storage. Such computerprograms, when executed, enable the system 565 to perform variousfunctions. The memory 540, the storage, and/or any other storage arepossible examples of computer-readable media.

The architecture and/or functionality of the various previous figuresmay be implemented in the context of a general computer system, acircuit board system, a game console system dedicated for entertainmentpurposes, an application-specific system, and/or any other desiredsystem. For example, the system 565 may take the form of a desktopcomputer, a laptop computer, a tablet computer, servers, supercomputers,a smart-phone (e.g., a wireless, hand-held device), personal digitalassistant (PDA), a digital camera, a vehicle, a head mounted display, ahand-held electronic device, a mobile phone device, a television,workstation, game consoles, embedded system, and/or any other type oflogic.

Machine Learning

Deep neural networks (DNNs) developed on processors, such as the PPU 300have been used for diverse use cases, from self-driving cars to fasterdrug development, from automatic image captioning in online imagedatabases to smart real-time language translation in video chatapplications. Deep learning is a technique that models the neurallearning process of the human brain, continually learning, continuallygetting smarter, and delivering more accurate results more quickly overtime. A child is initially taught by an adult to correctly identify andclassify various shapes, eventually being able to identify shapeswithout any coaching. Similarly, a deep learning or neural learningsystem needs to be trained in object recognition and classification forit get smarter and more efficient at identifying basic objects, occludedobjects, etc., while also assigning context to objects.

At the simplest level, neurons in the human brain look at various inputsthat are received, importance levels are assigned to each of theseinputs, and output is passed on to other neurons to act upon. Anartificial neuron or perceptron is the most basic model of a neuralnetwork. In one example, a perceptron may receive one or more inputsthat represent various features of an object that the perceptron isbeing trained to recognize and classify, and each of these features isassigned a certain weight based on the importance of that feature indefining the shape of an object.

A deep neural network (DNN) model includes multiple layers of manyconnected perceptrons (e.g., nodes) that can be trained with enormousamounts of input data to quickly solve complex problems with highaccuracy. In one example, a first layer of the DLL model breaks down aninput image of an automobile into various sections and looks for basicpatterns such as lines and angles. The second layer assembles the linesto look for higher level patterns such as wheels, windshields, andmirrors. The next layer identifies the type of vehicle, and the finalfew layers generate a label for the input image, identifying the modelof a specific automobile brand.

Once the DNN is trained, the DNN can be deployed and used to identifyand classify objects or patterns in a process known as inference.Examples of inference (the process through which a DNN extracts usefulinformation from a given input) include identifying handwritten numberson checks deposited into ATM machines, identifying images of friends inphotos, delivering movie recommendations to over fifty million users,identifying and classifying different types of automobiles, pedestrians,and road hazards in driverless cars, or translating human speech inreal-time.

During training, data flows through the DNN in a forward propagationphase until a prediction is produced that indicates a labelcorresponding to the input. If the neural network does not correctlylabel the input, then errors between the correct label and the predictedlabel are analyzed, and the weights are adjusted for each feature duringa backward propagation phase until the DNN correctly labels the inputand other inputs in a training dataset. Training complex neural networksrequires massive amounts of parallel computing performance, includingfloating-point multiplications and additions that are supported by thePPU 300. Inferencing is less compute-intensive than training, being alatency-sensitive process where a trained neural network is applied tonew inputs it has not seen before to classify images, translate speech,and generally infer new information.

Neural networks rely heavily on matrix math operations, and complexmulti-layered networks require tremendous amounts of floating-pointperformance and bandwidth for both efficiency and speed. With thousandsof processing cores, optimized for matrix math operations, anddelivering tens to hundreds of TFLOPS of performance, the PPU 300 is acomputing platform capable of delivering performance required for deepneural network-based artificial intelligence and machine learningapplications.

While various embodiments have been described above, it should beunderstood that they have been presented by way of example only, and notlimitation. Thus, the breadth and scope of a preferred embodiment shouldnot be limited by any of the above-described exemplary embodiments, butshould be defined only in accordance with the following claims and theirequivalents.

What is claimed is:
 1. A circuit, configured to: receive an input valuerepresented by a first number of bits; identify a portion of the firstnumber of bits of the input value as a rounding value represented by asecond number of bits; extract a second value from the input value;align the rounding value with a rounding position within the secondvalue, wherein the rounding position corresponds to a least significantbit of an output value represented by a third number of bits; add thealigned rounding value and the second value to produce a sum; andtruncate a fourth number of bits from the sum to produce the outputvalue.
 2. The circuit of claim 1, wherein the third number of bits isless than the first number of bits.
 3. The circuit of claim 1, wherein afraction value replaces the rounding value when the input value isgreater than a threshold value.
 4. The circuit of claim 1, wherein theinput value is a mantissa of a floating-point format number.
 5. Thecircuit of claim 1, wherein the second number bits and the fourth numberof bits are the same.
 6. The circuit of claim 3, wherein the fractionvalue is one of a fixed value, a programmed value, and a computed value.7. The circuit of claim 1, wherein a fraction value replaces therounding value when the input value is within a threshold range.
 8. Thecircuit of claim 1, wherein a fraction value replaces the rounding valuebased on a rounding mode.
 9. The circuit of claim 1, wherein, prior toaligning the rounding value, the rounding value is modified based on afraction value that is one of a fixed value, a programmed value, or acomputed value.
 10. The circuit of claim 9, wherein the rounding valueis bitwise exclusive ORed with the fraction value.
 11. The circuit ofclaim 9, wherein the rounding value is bitwise rotated according to thefraction value.
 12. The circuit of claim 9, wherein the rounding valueis bitwise ANDed with the fraction value.
 13. The circuit of claim 1,wherein the rounding value comprises the second number of leastsignificant bits of the input value.
 14. The circuit of claim 13,wherein the second number of bits is eight.
 15. The circuit of claim 1,wherein the input value is a mantissa of a floating-point format numberand the output value is an integer.
 16. The circuit of claim 1, whereinat least one of the input value, the first number of bits, the secondnumber of bits, and the third number of bits is included as an operandof a conversion instruction.
 17. The circuit of claim 16, wherein theinstruction is a format conversion instruction.
 18. The circuit of claim16, wherein the instruction is an arithmetic operation instruction. 19.A method, comprising: receiving an input value represented by a firstnumber of bits; identifying a portion of the first number of bits of theinput value as a rounding value represented by a second number of bits;extracting a second value from the input value; aligning the roundingvalue with a rounding position within the second value, wherein therounding position corresponds to a least significant bit of an outputvalue represented by a third number of bits; adding the aligned roundingvalue and the second value to produce a sum; and truncating a fourthnumber of bits from the sum to produce the output value.
 20. Anon-transitory, computer-readable storage medium storing instructionsthat, when executed by a processing unit, cause the processing unit to:receive an input value represented by a first number of bits; identify aportion of the first number of bits of the input value as a roundingvalue represented by a second number of bits; extract a second valuefrom the input value; align the rounding value with a rounding positionwithin the second value, wherein the rounding position corresponds to aleast significant bit of an output value represented by a third numberof bits; add the aligned rounding value and the second value to producea sum; and truncate a fourth number of bits from the sum to produce theoutput value.